Sample Preparation - package opening, silicon access, etc...

Solutions for Sample Preparation

Enabling your Physical analysis:

Package opening, Cross section, Backside Silicon access, Metrology, Delayering






Sample preparation for failure analysis & counterfeit study is required in many different ways:

Package Opening Package opening/ Decapsulation is standard for package physical failure analysis, counterfeit, or just to access silicon.
Delayering Delayering enables access to probing solution or any analysis on front side silicon (like counterfeit)
Backside Silicon Access Advanced backside silicon access is require to enable backside microscopy and laser techniques, using backside silicon thinning on wafer/ package, but also to support your physical failure analysis on silicon

Backside silicon metrology is enabling controlling your different sample preparation


Providing flexibility to address your needs & challenges

Here are reviews of challenges & solutions regarding :

Package OpeningPackage Opening - Decapsulation

Package opening or de-capsulation need flexibility to address the different package and materials. In addition, it requires new capabilities to address new technologies, for instance to address de-capsulation without damaging copper wine.

Sector Technologies offer a complementary suite for wet package opening from Nisene’s technology.

  • JetEtch for acid de-capsulation – with the latest JetEtch Pro, it is the most suitable solution for your latest IC and selectivity you require.
  • New! JetEtch with Copper Protection - the lastest JetEtch Pro Cu Protect, introduce unique & efficient technologies that does not require laser pre-opening.
Package opening - De-capsulation bond pad Copper Wires copper wire - SEM image

Multi layer die showing second bond exposure (JetEtch)

Bond pad view after chemical opening (JetEtch) Copper wires after JetEtch Pro Cu Protect opening

Copper wires after JetEtch Pro Cu Protect opening

Sector Technologies is also offering Laser Pre-opening solution

  • LRay is best cost efficient solution for pre-opening of IC package, including ceramics... Its new fiber laser technology enable best economical & reliable choice - with Decap 10 table top solution or the flexible Decap 20 solution.

Laser Opening

Laser dry Pre-opening of IC Package



Backside Silicon AccessBackside silicon access


LACE trench on the silicon backside allowing FIB edit on the floor of the trench


More and more solutions requires a clean access to the backside silicon:  FIB backside, all emission microscope solution (see our EFA tool), as well as physical access t

o flip-chip. Localize silicon access is required for instance as soon as you need to preserve electrical capabilities, whereas polishing is thinning full die.

Challenge is to enable a clean and fast localised access through Silicon.

Sector Technologies solution, thanks to our partner Varioscale, enable quick clean access for your analysis.

  • Check the unique LACE (Laser Assisted Chemical Etching) product available in the market. Providing sample preparation solution scaling between "decapsulation" & "FIB".
    • 50x faster than FIB
    • Clean Etch: turning Silicon in vapor (i.e. no particle being generated).
    • Precise Etch as close as <1µm to the active area - enabling probing. Solution includes in-situ metrology technology.
    • With additional large scale deposition flexibility

Metrologie solutions

Newest technologies need a tighter control on dimension:

  • EFA backside techniques are using SIL (Solid Immersion Lenses), where backside thickness need to be controled
  • MEMS reliability is impacted by warping
  • MEMS access need as well controls - at the expense/ risk of getting through cavities
  • FIB backside need to be prepare with some silicion

Any ellipsometer may not be appropriate to accomodate your different silicon doping/ surface condition.

Sector Technologies offer, thanks to our partner Varioscale, metrology solution, enabling through silicon & oxide.

  • To efficiently control of your backside Silicon thickness, regardless of the surface condition/ Silicon doping

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