Solutions for Sample Preparation
Enabling your Physical analysis:
Package opening, Delayering, Cross section, Backside Silicon access, Metrology
Sample preparation for failure analysis & counterfeit study is required in many different ways:
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Package opening/ Decapsulation is standard for package physical failure analysis, counterfeit, or just to access silicon. | |
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Delayering enables access to probing solution or any analysis on front side silicon (like counterfeit) | |
| Cross sectioning support package physical failure analysis and visualization of your defects | ||
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Advanced backside silicon access is require to enable backside microscopy and laser techniques, using backside silicon thinning on wafer/ package, but also to support your physical failure analysis on silicon | |
| Backside silicon metrology is enabling controlling your different sample preparation |
Providing flexibility to address your needs & challenges
Here are reviews of challenges & solutions regarding :
Package Opening - Decapsulation
Package opening or de-capsulation need flexibility to address the different package and materials. In addition, it requires new capabilities to address new technologies, for instance to address de-capsulation without damaging copper wine.
Sector Technologies offer a complementary suite for package opening from Nisene’s technology.
- JetEtch for acid de-capsulation – with the latest JetEtch II, it is the most suitable solution for your latest IC and selectivity you require.
- FA-LIT for laser de-capsulation & cross sectioning on package – with is patented technologies, it is enabling you removing gels and preserving copper wires. Laser has ability to cut through lead frame, any material usually not accessible to chemistry.
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| Multi die package -opening showing second bond exposure (JetEtch) |
Bond pad view after chemical opening (JetEtch) | FA-LIT Laser opening | Wires & connections view after FA-LIT Laser opening |
Delayering
Especially, for delayering, challenge is to ensure selectivity of the layer removed.
Sector Technologies offer unique wet chemistry for delayering to enable individual layer selectivity and ensuring planar process.
- Omnietch from Nisene’s technology introduced GelEtch technologies (1) to improve etching over standard wet etch (trhough better absorption of the etchant) and (2) to address challenges like copper removal.
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Example of delayering of a copper layer. On the top view, cross section seen in SEM is clearly showing that Cu interconnect is not remove (if chosen to). |
Cross-Sectionning
Depending on scaling of your cross-section and your request
- FA-LIT’s laser from Nisene Technologies will enable cross-sectionning on your package without putting physical stress on device.
- Non Destructive cross sectioning is possible: using Xradia’s 3D Xray tomography, enabling cross sectioning your entire device at highest resolution (regardless your package size).
- DCG’s FIB solution, eventhough dedicated to circuit edit – it would enable your FIB cut on your device.
Backside silicon access
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| LACE trench on the silicon backside allowing FIB edit on the floor of the trench |
More and more solutions requires a clean access to the backside silicon: FIB backside, all emission microscope solution (see our EFA tool), as well as physical access to flip-chip. Localize silicon access is required for instance as soon as you need to preserve electrical capabilities, whereas polishing is thinning full die.
Challenge is to enable a clean and fast localised access through Silicon.
Sector Technologies solution, thanks to our partner Varioscale, enable quick clean access for your analysis.
- Check VarioEdit, the unique LACE (Laser Assisted Chemical Etching) product available in the market. Providing sample preparation solution scaling between "decapsulation" & "FIB".
- 50x faster than FIB
- Clean Etch: turning Silicon in vapor (i.e. no particle being generated).
- Precise Etch as close as <1µm to the active area - enabling probing. Solution includes in-situ metrology technology.
- With additional large scale deposition flexibility
Metrologie solutions
Newest technologies need a tighter control on dimension:
- EFA backside techniques are using SIL (Solid Immersion Lenses), where backside thickness need to be controled
- MEMS reliability is impacted by warping
- MEMS access need as well controls - at the expense/ risk of getting through cavities
- FIB backside need to be prepare with some silicion
Any ellipsometer may not be appropriate to accomodate your different silicon doping/ surface condition.
Sector Technologies offer, thanks to our partner Varioscale, metrology solution, enabling through silicon & oxide.
- To efficiently control of your backside Silicon thickness, regardless of the surface condition/ Silicon doping
- For more information on VarioMetric (VMT) or VarioProfile (VMP) solution